Demand for relatively faster semiconductor systems is on the rise in response to improvements in semiconductor integration density. Synchronous devices operating in synchronization with external clock signals are often used to improve the operation speed of semiconductor devices.
Single data rate (SDR) synchronous semiconductor devices have been used in the past to address the demand for improved the operation speed. The SDR synchronous semiconductor devices may receive as an input or generate as an output data through a single data pin in synchronization with every rising edge of an external clock signal.
However, there is an increase in demand for high performance semiconductor devices operating at relatively higher speeds than the SDR synchronous semiconductor devices to accommodate relatively higher performance semiconductor systems. Double data rate (DDR) synchronous semiconductor devices evolved to address the needs of such high performance semiconductor systems. The DDR synchronous semiconductor devices may receive as an input or generate as an output data in synchronization with every rising edge and with every falling edge of an external clock signal. This enables DDR synchronous semiconductor devices to operate at approximately twice the speed of SDR synchronous semiconductor devices in response to an external clock signal having substantially the same frequency as an external clock signal used by SDR synchronous devices.